1. Field of the Invention
The present invention relates generally to a multi-chip stack structure and fabrication method thereof, and more particularly to a leadframe-type multi-chip stack structure and fabrication method thereof.
2. Description of Related Art
Currently, multi-chip module (MCM) semiconductor packages with improved performance and capacity have been developed for meeting demand for high integration and miniaturization of packages, thereby facilitating fabrication of portable and multifunctional electronic products with high performance. Typically, a multi-chip module semiconductor package comprises at least two chips stack disposed to a chip carrier.
FIGS. 1A to 1D show a fabrication method of a leadframe-type multi-chip stack structure disclosed by U.S. Pat. No. 5,545,922. First, as shown in FIG. 1A, a leadframe 10 having a die base 101 and a plurality of leads 102 disposed around the die base 101 is provided, and a first chip 11 is disposed to a first surface of the die base 101 through a die bonding process. Subsequently, as shown in FIG. 1B, the leadframe 10 is upside-down disposed to a support block 13 having a cavity 130, wherein the leads 102 are supported by the support block 13 and the first chip 11 is received in the cavity 130, and a second chip 12 is further disposed to a second surface of the die base 101. Then, the leadframe 10 mounted with the first and second chips 11, 12 is disposed on a first heating block 15 having a first cavity 150 with the leads 102 pressed by clamping blocks 14 and the second chip 12 received in the first cavity 150. Thereafter, a first wire bonding process is performed so as to form a plurality of first bonding wires 161 electrically connecting the first chip 11 to the leads 102, wherein stitch bonds are formed at positions where the first bonding wires 161 are bonded the leads 102. Further, the stitch bonds are supported by the heating block 15 such that sufficient heat can be provided by the first heating block 15 for efficiently bonding the first bonding wires 161 and the leads 102, as shown in FIG. 1C. Then, the leadframe 10 is upside-down disposed to a second heating block 17 with the leads 102 supported by the second heating block 17, and a second wire bonding process is performed so as to form a plurality of second bonding wires 162 electrically connecting the second chip 12 and the leads 102, wherein the first chip 11 and the first bonding wires 161 are received in a second cavity 170 of the second heating block 17. Similarly, stitch bonds of the second bonding wires 162 bonding the leads 102 are supported by the second heating block 17 such that sufficient heat can be provided by the second heating block 17 for efficiently bonding the first bonding wires 161 and the leads 102. Meanwhile, the stitch bonds of the second bonding wires 162 offset from the stitch bonds of the first bonding wires 161, as shown in FIG. 1D.
In the above-mentioned multi-chip stack structure, two heating blocks are needed and the wire bonding positions need to be changed on opposite sides of the leadframe, which not only increases the fabrication time but also increases the fabrication expense. Further, as bonding position of the second bonding wires on the leadframe need to be offset outward corresponding to the second heating block, the length of the bonding wires is increased, thereby adversely affecting the electrical performance of the whole structure and meanwhile increasing the whole package size. Furthermore, the first and second chips may not match due to electrical function difference therebetween.
Therefore, how to overcome the above drawbacks has become urgent.